1. Field of the Invention
The invention concerns analogue-digital converters, in other words electronic circuit capable of converting an analogue input signal into a precise digital value representing the amplitude of the analogue signal. The digital value is obtained in the form of a word containing several bits, generally coded in pure binary.
2. Description of the Prior Art
There are several conversion procedures, and the choice of one procedure rather than another depends on the performances required from the converter. The most important parameters for these performances are:
the resolution, defined by the number of bits in the output word precisely representing the amplitude of the analogue signal; the number of bits may be 16 or 18, or even 20 for the most accurate converters, and the precision is generally + or -1/2 of the least significant bit; PA1 the speed, in other words the number of conversion operations that can be done in one second; PA1 the power consumption; a fast and accurate converter consumes much more energy than a slow and inaccurate converter; the power consumption increases the temperature of the chip in the integrated circuit on which the converter is made. This temperature rise must be compensated by cooling equipment that make the circuit difficult to use when there are dimensional constraints to be respected; PA1 and obviously the cost of design and manufacture of the converter, in particular related to the surface area of the chip in the integrated circuit used by the converter. PA1 successive approximation converters that successively compare the input analogue signal Vin with digital values that get a little closer to the value of the analogue signal on each iteration; these converters work in at least N phases if the value is coded on N bits; they are therefore generally very slow for precisions exceeding 6 or 8 bits. PA1 "flash" converters that use 2.sup.N comparators in parallel; each comparator receives firstly the analogue signal, and secondly one of the 2.sup.N reference voltages defined by a bridge of 2.sup.N precision resistances; these converters are very fast (generally 2 phases) but they are very large and consume a large amount of power when N is equal to 10 or 12 bits; PA1 combined converters with a coarse converter to obtain high order bits and a fine converter to obtain low order bits; the coarse converter may be fast and imprecise (for example 4 to 6 bits), whereas the fine converter must be precise even if it is slower. PA1 the first two rank k-1 interpolation signals varying as a function of Vin in phase opposition, applied as inputs to the first differential pair, PA1 these same signals, crossed, applied to the second differential pair, PA1 the other two rank k-1 interpolation signals applied to the third differential pair. PA1 a first and second rank k-1 interpolation signal varying 90.degree. out of phase of Vin, applied as input to the first differential pair, PA1 the same signals but crossed, applied to the inputs of the second differential pair, PA1 a third rank k-1 interpolation signal, varying in phase opposition with the first, is applied to an input of the third differential pair, the second rank k-1 interpolation signal being applied to the other input of the third pair. PA1 on the first differential pair, output signals from the first differential amplifier varying in phase opposition to Vin, and cancelling out when Vin is equal to the first main voltage reference VR(i-1 ); PA1 on the second differential pair, output signals from the third amplifier varying in phase opposition and cancelling out when Vin is equal to the third main voltage reference VR(i+1); PA1 on the third differential pair, output signals from the second amplifier, also varying in phase opposition and cancelling out for the second voltage reference VR(i). PA1 on the first differential pair, an output from the third amplifier and an output from the second, PA1 on the second differential pair, the same signals but crossed, PA1 on the third pair, firstly an output from the first amplifier, and secondly an output from the second amplifier.
The qualities of an analogue-digital-converter are the result of a compromise between the above parameters, and the purpose of this invention is to improve this compromise.
Some known analogue-digital converter structures are:
Several solutions have already been put forward for combined converters.
In one solution, the coarse converter is a flash converter that supplies the P high order bits. This value is reconverted into an analogue signal by a P-bit digital-analogue converter; the difference between the analogue signal Vin and this reconverted value, also called the remainder or residue, is converted by a fine converter that determines the low order bits of the conversion; this consumes less power and is more compact than a flash converter, but the digital-analogue conversion takes time and requires precise servocontrol of gains in the various parts of the circuit (analogue-digital and digital-analogue converter).
In another combined converter architecture, an input analogue signal "folding" converter is used; the input signal Vin is applied to at least two foldback circuits that have the function of supplying "folded" signals Vr1, Vr1b, Vr2, Vr2b having an amplitude that varies with the amplitude of the input signal Vin in accordance with a periodic function (with a near-sinusoidal shape); the period is defined by the difference between the reference voltage values uniformly distributed between two extreme values; the reference voltages are produced by a resistant bridge, and the number of reference voltages used by foldback blocks defines the number of periods of the folded signal in the maximum possible variation range of the input analogue signal. Functions Vr1 and Vr1b are in phase opposition, in other words the signal Vr1b is minimum for the value of Vin for which Vr1 is maximum, and vice-versa. The same is true for Vr2 and Vr2b. Functions Vr1 and Vr2 are 90.degree. out of phase, in other words the folded signal Vr2 is maximum or minimum for the input value Vin for which Vr1 is zero, and vice versa.
Periodic maxima and minima are actually equal to reference voltages used by the foldback circuits, the reference voltages used by the first foldback circuit being regularly alternated with reference voltages used by the second foldback circuit. Differences (Vr1-Vr1b), (Vr2-Vr2b) between folded signals from the two blocks periodically cancel out for values of the input voltage equal to the reference voltages; these differences are used to create "interpolated" signals with the same general shape as the differences between folded signals, but that cancel out for input voltage values intermediate between the reference values.
Thus, starting from an input signal Vin and a series of uniformly distributed reference voltages, at least four folded signals Vr1, Vr1b, Vr2, Vr2b are created, the amplitude of which depends on Vin (but in the form of a periodic function) and several periodic interpolated signals, for which the positive or negative sign depends on the difference between Vin and reference voltage values intermediate between the initial references.
Interpolated signals can then be used to obtain the low order of the digital-analogue conversion representing the position of Vin with respect to these adjacent intermediate reference values. High orders are given by a coarse converter that indicates the folded signal "period" within which the analogue input voltage Vin is located, in other words it indicates the adjacent reference voltage values between which Vin is located. The advantage if this architecture lies in the fact that interpolation circuits receive voltages (differences of folded signals) whose amplitudes depend on the exact value of the input voltage Vin but are independent of the range in which Vin is located. Consequently a single interpolation circuit is sufficient to establish low orders of the conversion, without it being necessary to use a digital-analogue converter, therefore without slowing down the conversion operation and without any gain servocontrol problems.
In an existing architecture, the interpolation circuit consists of single resistance bridges that for example receive the differences (Vr1-Vr2) and (Vr1b-Vr2b) between folded signals. Intermediate taps points on these resistance bridges output interpolated signals; they are applied in pairs to comparators that toggle in one of two directions depending on the value of the interpolated signals and therefore depending on the position of Vin between two adjacent reference voltages.
In another architecture, the interpolation circuit contains several stages in cascade; the first stage receives the four folded signals and combines them to produce four other signals that are still periodic functions of the input analogue voltage Vin, but this time with a period double the period of the folded signals; these new signals pass through zero not only when Vin is equal to the reference voltages used for the foldback, but also for intermediate reference voltages located at the mid-point of the interval between two adjacent reference voltages. Therefore the signals can supply one information bit more than the high order bits obtained by the coarse converter. Voltages thus obtained at the output of the first stage are applied to a second stage that performs the same function (creation of signals with a newly doubled period) and which supplies an additional bit for the value of Vin. Several stages may be put in cascade in this way to obtain the successive low order bits of the conversion. U.S. Pat. No. 5 126 742 would appear to describe an architecture of this type.
Regardless of whether interpolation circuits are parallel interpolation circuits (application of folded signals to resistance bridges) or cascade interpolation circuits, the major disadvantage of input analogue signal foldback architectures is the disadvantage inherent to the circuits that perform the foldback; it is impossible to make a folded signal that is genuinely symmetrical about a mean value.
The operation of interpolation circuits on the output side of foldback circuits is based largely on the very precise symmetry of the four foldback signals. Even a slight asymmetry between the maximum and minimum values of a folded signal will shift intermediate voltage values for which the folded signal differences cancel out. Since these values are used as a reference for the conversion of low orders, this can create conversion errors that may be high.
These symmetry errors may be partially compensated by additional circuits, but this makes the circuit more complex, larger and less reliable.
Signal foldback analogue-digital converters also require a coarse converter to indicate the reference voltage values between which the input voltage is located, and it is difficult to combine information output from the coarse converter with information output from the folded signal interpolation, particularly to take account of cases in which the voltage to be converted is close to the limit between two consecutive digital values output by the coarse converter; it is sometimes necessary to correct the high order bits as a function of the low order bits.